1. Technical Field
The present invention relates to a test apparatus and a test method.
2. Related Art
A known test apparatus designed for testing a device under test such as a semiconductor chip includes a plurality of test circuits that operate in synchronization with each other (for example, see Patent Documents 1 and 2).
Patent Document 1: International Publication No. 2003/062843 Pamphlet
Patent Document 2: Japanese Patent Application Publication No. 2007-052028
A plurality of test circuits in a test apparatus operate in accordance with programs, sequences and the like provided thereto in advance. The test apparatus synchronously starts and suspends the execution of the programs, sequences and the like, so that the respective test circuits operate in synchronization with each other.
When the test apparatus is configured to perform a variety of tests, however, synchronizing the execution start timings of the programs at the respective test circuits may not be sufficient to synchronously perform the various tests. For example, there may be a case where the test circuits may desire to perform a particular step in synchronization with each other on condition that a predetermined test circuit detects a failure while the test circuits are executing programs. Furthermore, when the test apparatus is designed to perform a variety of tests including a test utilizing an analog circuit, the test circuits that are required to operate in synchronization with each other include an analog circuit.